Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device includes a substrate which has a main surface, a back surface, and a through hole. The semiconductor device also includes an insulating film formed on an inner wall of the through hole, a conductive member provided on the insulating film within the through hole, an external terminal provided above the main surface, and a wiring portion connected to the external terminal. The semiconductor device also includes an encapsulating layer which covers the main surface and the wiring portion except for a portion to which the external terminal is connected. A side surface of the encapsulating layer is formed inside a side surface of the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a packagestructure and a method of manufacturing the same.

This application is counterpart of Japanese patent applications, SerialNumber 404987/2003, filed Dec. 3, 2003, the subject matter of which isincorporated herein by reference.

2. Description of the Related Art

There has recently been an increasingly demand for a reduction andthinning of an outer size (package size) of a semiconductor devicemounted to electronic equipment such as a portable device. With itsdemand, there has been proposed a CSP (Chip Size Package) correspondingto a semiconductor device packaged to an outer size substantiallyidentical to an outer size of a semiconductor chip.

In terms of a reduction in the manufacturing cost, attention is nowgiven, as one form of CSP, to a WCSP (WaferLevel Chip Size Package orWaferLevel Chip Scale Package) obtained by fractionalization through theuse of dicing or the like after processes up to an external terminalforming process have been completed in a wafer state (see, for example,a patent document 1).

There is also known a bear chip having a configuration equipped withthrough portions in which conductors are formed on inner wall surfacesof through holes that pass between the obverse and reverse sides of asubstrate (see, for example, a patent document 2). Since thetransmission of a signal between the front and back surfaces of the bearchip is enabled by virtue of the through portion, laminated packageslaminated in plural form in the direction of thickness of the bear chipcan be configured.

Such through portions are normally formed in peripheral edge portions,i.e., dicing areas of chips cut out by dicing using a blade. This isbecause since there is a need to lay out circuit elements in the highdensity in a circuit element forming area (also called “active area”)surrounded by the dicing areas, there is no space for each throughportion, and the through portions are formed in the active area, therebycausing the fear of the scale-up of a chip size and an increase inmanufacturing cost. Incidentally, the dicing areas used herein meanssurfaces to be cut off by dicing and areas located in the neighborhoodthereof.

Patent Document 1

Japanese Laid Open Patent Application No. 2002-110951

Patent Document 2

Japanese Laid Open Patent Application No. 2000-243900

However, cracks and chipping-off are easy to take place in each dicingarea due to the shock of the blade at the dicing. Therefore; there was afear that the through portions formed in the dicing area were damageddue to the occurrence of such cracks and chipping-off or the like,thereby causing degradation of reliability. Particularly when microcracks has occurred in each dicing area, it was difficult todiscriminate the through portions subjected to the damage from outwardappearance. Thus, it was very difficult to manage the quality of eachchip.

In the wafer's dicing used up to now, the back surface of a wafer wasfixed onto a dicing sheet and thereafter the wafer was cut off from theexposed surface of the wafer by use of a blade. Therefore, theoccurrence of cracks and chipping-off greatly take place on the backside of the wafer in particular due to wafer's vibrations developed bythe blade, thereby causing the damage of the through portions.

Therefore, three has been proposed a method of expanding the spacing orinterval of a through portion between adjacent chips and ensuring itsufficiently in order to avoid the damage of the through portions due tothe cracks and chipping-off. Since, however, the number of chipscuttable per wafer is reduced due to the expansion of the width of eachdicing area, the manufacturing cost will increase.

Although there has heretofore been proposed a method utilizing heatfusion using laser light as the dicing method using the laser light,there are a lot of problems to be solved such as thermal distortion,contamination, etc.

SUMMARY OF THE INVENTION

Thus, the present invention has been made to solve the foregoingproblems. It is a principal object of the present invention to provide asemiconductor device having high reliability and high productivitywithout expanding a package size than ever, and a manufacturing methodthereof.

According to one aspect of the present invention, there is provided asemiconductor device, comprising:

-   -   a substrate which has a main surface including a central area        formed with a circuit element and an electrode pad connected to        the circuit element and a peripheral area surrounding the        central area, which has a back surface opposite to the main        surface, and which has a through hole defined in the peripheral        area and extending from the main surface to the back surface;    -   an insulating film formed on an inner wall of the through hole;    -   a conductive member provided on the insulating film within the        through hole and electrically connected to the circuit element;    -   an external terminal provided above the main surface;    -   a wiring portion which connects the external terminal and the        electrode pad; and    -   an encapsulating layer which covers the main surface and the        wiring portion except for a portion to which the external        terminal is connected,    -   wherein a side surface of the encapsulating layer is formed        inside a side surface of the substrate.

According to another aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising thefollowing steps of, upon cutting a plate-shaped object to be processedto fractionalize the same into a plurality of packages, therebyfabricating each individual semiconductor device:

-   -   preparing the object comprising:        -   a substrate including a main surface having a central area            formed with circuit elements and electrode pads connected to            the circuit elements, and a peripheral area that surrounds            the central area; a back surface opposite to the main            surface; and through holes which are defined in the            peripheral area and extend therethrough from the main            surface to the back surface;    -   an insulating film formed on inner walls of the through holes;    -   conductive members provided on the insulating film lying within        the through holes and respectively electrically connected to the        circuit elements;    -   external terminals provided above the main surface;    -   wiring portions that electrically connect the external terminals        and the electrode pads respectively; and    -   an encapsulating layer that covers the wiring portions and the        main surface from thereabove with surfaces being in touch        between the external terminals and the wiring portions being        left behind,    -   performing the cutting of the substrate by an unheated system        using laser light; and    -   carrying out the cutting of the encapsulating layer by a blade.

According to such a configuration, the side faces of the encapsulatinglayer are respectively formed inside the side faces of the substrate.

According to yet another aspect of the present invention, there isprovided a method of manufacturing a semiconductor device, comprisingthe following steps of, upon cutting a plate-shaped object to beprocessed to fractionalize the same into a plurality of packages,thereby fabricating each individual semiconductor device:

-   -   preparing the object comprising:    -   a substrate, said substrate including a semiconductor support        substrate, an insulating film formed on the semiconductor        support substrate, and a semiconductor layer formed on the        insulating film, said semiconductor layer having a main surface        including a central area formed with circuit elements and        electrode pads connected to the circuit elements and a        peripheral area that surrounds the central area;    -   trench portions defined in the peripheral area, which extend        from the main surface of the substrate to the support substrate;    -   conductive members provided within the trench portions and        electrically insulated from the semiconductor layer, said        conductive members being electrically connected to the circuit        elements and the semiconductor layer respectively;    -   external terminals provided above the main surface;    -   wiring portions that electrically connect between the external        terminals and the electrode pads; and    -   an encapsulating layer that covers the wiring portions and the        main surface from thereabove with surfaces being in touch        between the external terminals and the wiring portions being        left behind,    -   performing the cutting of the substrate by an unheated system        using laser light; and    -   carrying out the cutting of the encapsulating layer by using a        blade.

The side faces on the substrate side can be formed by cutting thesubstrate using laser dicing of an unheated system (or also called“non-melting system”) using laser light. In the laser dicing of theunheated system, a member to be cut can be cut off without almostproducing cracks and chipping-off therein. High-speed dicing is enabledas compared with the conventional dicing method using the blade.

As a result, it is possible to suppress suffering of damage of throughportions provided in a substrate in a dicing area and degradation ofreliability of each cut-out semiconductor device, both of which havebeen produced as before.

In addition, there is no need to expand the spacing or interval of athrough portion provided between adjacent semiconductor devices in orderto avoid the damage of each through portion by such dicing. It istherefore unnecessary to expand the width of the dicing area than ever.

Thus, a semiconductor device excellent in reliability and productivitycan be obtained without the number of semiconductor devices cuttable perwafer.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming the subject matter which is regarded as theinvention, it is believed that the invention, the objects and featuresof the invention and further objects, features and advantages thereofwill be better understood from the following description taken inconnection with the accompanying drawings in which:

FIG. 1 is a schematic plan view showing part of a wafer prior to beingdiced into semiconductor devices each according to a first embodiment ofthe present invention;

FIGS. 2(A) and 2(B) are respectively process views (part 1) fordescribing a process for manufacturing the semiconductor deviceaccording to the first embodiment of the present invention;

FIGS. 3(A) and 3(B) are respectively process views (part 2) fordescribing a process for manufacturing the semiconductor deviceaccording to the first embodiment of the present invention;

FIGS. 4(A) and 4(B) are respectively process views for describing aprocess for manufacturing a semiconductor device according to a secondembodiment of the present invention;

FIG. 5 is a schematic bottom view showing part of a wafer prior to beingdiced into semiconductor devices each according to a third embodiment ofthe present invention;

FIGS. 6(A) and 6(B) are respectively process views (part 1) fordescribing a process for manufacturing the semiconductor deviceaccording to the third embodiment of the present invention; and

FIGS. 7(A) and 7(B) are respectively process views (part 2) fordescribing a process for manufacturing the semiconductor deviceaccording to the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will hereinafter bedescribed with reference to the accompanying drawings. Incidentally, thedrawings merely schematically show the sizes, shapes and positionalrelationships of respective components to such a degree that the presentinvention can be understood. Thus, the present invention is by no meanslimited to the illustrated examples. In order to make it easy tounderstand the drawings, hatchings indicative of cross-sections areomitted except for parts. Incidentally, embodiments to be describedbelow are simply preferred examples and illustrated numerical conditionsare by no means limited to them. Similar components illustrated in therespective drawings are respectively identified by the same referencenumerals, and the description of certain common components might beomitted.

<First Embodiment>

A first embodiment of the present invention will be explained withreference to FIGS. 1 through 3. FIG. 1(A) is a plan view schematicallyshowing part of a wafer prior to be diced into semiconductor deviceseach according to the present embodiment. FIG. 2(A) is a cross-sectionalview as seen in the direction indicated by arrows in the figure, of acut-away portion (i.e., a cross-section) obtained by cutting FIG. 1(A)along the dashed line II—II. FIGS. 2(B) through 3(B) are respectivelycross-sectional views following FIG. 2(A), for describing thesemiconductor device according to the present embodiment and a method ofmanufacturing the same. Incidentally, the illustrations of a secondwiring layer 36, lands 38 and a surface protective film 39 all formed onthe back surface of a substrate, are omitted in FIG. 1(A).

The present embodiment will explain, by way of example, a packagestructural body 50 in which WCSPs 10 each having a package structurecapable of constituting a laminated package are cut out, as an object ortarget to be processed which needs a dicing process.

First of all, as shown in FIG. 1(A), a wafer-shaped package structuralbody 50 (to be described later) in which process steps up to theformation of external terminals and lands (not shown) on the obverse andreverse sides of an object to be processed have been completed, isprepared as the object. Sub areas 35 cut out as WCSPs 10 (hereinaftersimply might be called “WCSPs” and see FIG. 3(B)) each having a packagestructure via an individualizing process to be described later arearranged in the package structural body 50 in matrix form.

Described specifically, peripheral edge portions of a surface area ofeach sub area 35 are peripheral areas (or also called dicing areas) 45having predetermined widths including cut surfaces a fractionalizedevery WCSPs 10. An area surrounded by the dicing areas 45 of each subarea 35 is a central area (or also called “circuit element formingarea”) 40 having circuit elements. Electrode pads 14 are disposed alongthe outer periphery of the circuit element forming area 40 everypredetermined intervals. Also the electrode pads 14 are. electricallyconnected to their corresponding solder balls 34 via a dedicated firstredistribution wiring layer 26 that extends toward the inside of thecircuit element forming area 40. Through portions (or also called“contact portions”) 55 (to be described later) included in the adjacentsub areas 35 are respectively placed in opposing relationship atpositions which interpose plane or surfaces a (or also called “cutsurfaces”) to be cut at the dicing areas 45.

Subsequently, the package structural body 50 will be explained withreference to FIG. 2(A).

Electrode pads 14 made of aluminum, which are electrically connected totheir corresponding circuit elements, are formed in their correspondingcircuit element forming area 40 of a main surface 12 a of a substrate 12that constitutes the package structural body 50. In the presentembodiment, the substrate 12 is configured as a silicon substrate. Afirst insulating layer 20 in which a passivation film 16 made up of asilicon nitride film and a protective film 18 made up of a polyimidefilm are sequentially laminated, is formed on the main surface 12 a ofthe silicon substrate 12 so as to expose parts of top faces of theelectrode pads 14. A second insulating layer 22 made up of a siliconoxide film is formed on a back surface 12 b opposite to the main surface12 a of the silicon substrate 12.

Further, the above-described through portions 55 are conductive columnarportions that penetrate between the main surface and back surface (12 aand 12 b) of the silicon substrate 12 in the dicing area 45. The throughportions 55 make it possible to make conductive between the obverse andreverse sides of the silicon substrate 12. As a result, the transfer ofinput/output signals between the obverse and reverse sides of the WCSP10 of each laminated package is enabled, and the WCSPs are laminated inthe thickness direction so that the laminated package can be configured.The through portions 55 are formed by, for example, forming the firstand second insulating layers (20, 22) in the main surface and backsurface (12 a and 12 b) of the silicon substrate and thereafter definingthrough holes (i.e., holes extending through the first and secondinsulating layers) 24 extending therethrough by a drill or the like.Thereafter, an insulating film 56 is coated on an inner wall (or alsocalled “on an internal surface”) of each through hole 24 by using aninsulating material (not shown), and a conductive member 57 such ascopper or the like is formed on the insulating film 56 by plating,whereby the corresponding through portion 55 is obtained.

The respective electrode pads 24 are electrically connected to both oreither one of one ends of the through portions 55 and one ends of postportions 28 constituting a wiring portion 32 via the first wiring layer26 used as a wring pattern constituting the wiring portion 32 formed onthe first insulating layer 20. That is, the wiring portion 32 in thepresent configurational example includes the first wiring layer 26extending in the direction parallel to the main surface 12 a of thesilicon substrate 12, and the post portion 28 that protrudes towardabove the first wiring layer 26 in the direction normal to the mainsurface 12 a. The wiring portion 32 constitutes a convex portion thatprotrudes in the direction normal to the main surface 12 a as a whole.One end of the wiring portion 32 is connected to the electrode pads 14,and the top face of the other end thereof is exposed without beingcovered with an encapsulating layer 42 to be described later. The otherend of the through portion 55 is electrically connected to lands 38 viaa second wiring layer 36 formed on the second insulating layer 22. Eachland 38 is provided on the second wiring layer 36 exposed from anopening defined in a surface protective film (or also called “solderresist film”) 39 that covers the entirety of the back surface 12 b ofthe silicon substrate 12. Incidentally, the first and second wiringlayers (26, 36) are formed of copper (Cu) and function as redistributionwiring layers capable of redistributing the post portions 28 and thelands 38 at desired positions respectively. Thus, the first and secondwiring layers (26 and 36) are also called “first and secondredistribution wiring layers” respectively. The encapsulating layer 42that covers the abovedescribed components (14, 20 and 32) is formed overthe whole main surface 12 a of the silicon substrate 12 with such athickness that the top faces of the post portions 28 are exposed. Solderballs 34 corresponding to external terminals are formed on theircorresponding top faces of the post portions 28 exposed from theencapsulating layer 42.

Owing to the above-described configuration, the transfer of input/outputsignals between the obverse and reverse sides is enabled and WCSPs eachcapable of constituting the laminated package is obtained by theirlamination in the thickness direction.

Described specifically, a signal outputted from a circuit element istransmitted to a path extending from the electrode pad 14 to the solderball 34 via the wiring portion 32 and a path extending from theelectrode pad 14 to the land 38 via the first wiring layer 26, throughportion 55 and second wiring layer 36. A signal inputted from each ofthe solder ball 34 and the land 38 is transmitted via paths opposite tothe above. Incidentally, the transmission paths are not limited to theabove-described paths and can be formed as various wiring pathsaccording to purposes and design.

Subsequently, the solder balls 34 included in the wafer-shaped packagestructural body 50 are fixed onto a dicing sheet 65. As the dicing sheet65, may be used, for example, one in which an ultraviolet cured acrylicresin used as an adhesive material is applied onto the surface of a basematerial made of polyolefin.

Subsequently, the wafer-shaped package structural body 50 is cut amongthe through portions 55 of the adjacent sub areas 35 in the followingprocedure so as to be brought into fractionization every package WCSPs10.

First of all, the silicon substrate 12 between the through portions 55of the adjacent sub areas 35 is cut along the surfaces a to be cut off.

Since the silicon substrate 12 has permeability relative to laser lightin the present embodiment, the cutting of the silicon substrate 12 isdone using a non-melting system (or also called “unheated processingsystem”) using laser light.

In the present configurational example, laser dicing of the nonmeltingsystem is carried out assuming that irradiation conditions for the laserlight, e.g., a light source is set as a YAG laser, the wavelength of thelaser light is set as 1064 nm and a spot sectional area of the laserlight is set as 3.14×10⁻⁸cm². Since infrared radiation is transmittedthrough the silicon substrate 12, the alignment at the irradiation ofthe laser light can be done by observing it with an infrared camera.Incidentally, the irradiation conditions for the laser light are notlimited to only the above but can be set arbitrarily and suitablyaccording to purposes and design.

Described specifically, laser light is applied along each surface a tobe cut off while a light convergence point of the laser light is beingfocused on a predetermined position lying inside the silicon substrate12.

On example of an apparatus for irradiating the laser light at this timetakes a configuration in which a condenser lens 74 is provided at apredetermined position between a laser light source 70 and an object ortarget 72 as shown in FIG. 1(B). According to such a configuration, thelaser light can be selectively concentrated on an arbitrary portion asviewed in the direction of depth of the object 72 by the condenser lens74 (light convergence point is expressed in P in the figure).

A modified portion 80 caused by multiple photon absorption is formed bylaser light gathered inside the silicon substrate 12 with high accuracy.At this time, a crack 82 with the modified portion 80 as its startingpoint occurs due to internal stress and distortion with the formation ofthe modified portion 80. That is, since the crack 82 occurs due to theiroccurrence occurs, the modified portion 80 is also referred to as acrack generation source.

Thus, the silicon substrate 12 can be cut using the crack 82 generatedalong the surface a. to be cut off in the dicing area 45 (see FIG.2(B)). Incidentally, although the crack 82 used here is used as athrough cut that extends from the back surface 12 b of the siliconsubstrate 12 to its main surface 12 a, it may be a half cut that doesnot reach the main surface 12 a of the silicon substrate 12. In such acase, predetermined dicing is thereafter additionally done to therebycut the silicon substrate 12. Incidentally, after the cutting of part ofthe silicon substrate 12, the encapsulating layer 42 havingnon-permeability hard to make the laser light transmissive remains inthe dicing area 45 without being cut.

Thereafter, a back surface 50 b opposite to the surface brought intocontact with the dicing sheet 65, of the package structural body 50 isabsorbed or sucked by a vacuum suction apparatus or a back surface 65 bof the dicing sheet 65 is sucked by the vacuum suction apparatus to peelthe dicing sheet 65 from the package structural body 50. Then the backsurface 50 b on the silicon substrate side, of the package structuralbody 50 is fixed onto a new dicing sheet 85 in which a bonding materialis applied onto the surface of a base material.

Next, the encapsulating layer 42 lying among the through portions 55 ofthe adjacent respective sub areas 35 is cut along the surfaces a to becut off.

Since the encapsulating layer 42 has non-permeability hard to make thelaser light transmissive in the present embodiment, it is cut using ablade rotated at high speed.

As the blade used herein, is used, for example, a blade to which diamondfine grains whose diameters lying within a range of from 20 μm to 30 μmare taken up in large numbers at outer peripheral portions of ametal-made disc, are fixedly secured. In the present configurationalexample, the cutting of the passivation film 16 and the protective film18 provided on the silicon substrate 12 is done in conjunction with thecutting of the encapsulating layer 42. Incidentally, since various filmscan be formed over the silicon substrate 12 in each dicing area 45,either the dicing using the laser light or the dicing using the bladecan be done selectively in consideration of the permeability or the likeof the films with respect to the laser light.

Consequently, the blade (not shown) rotated about its axis at high speedis pressed against the surface of the encapsulating layer 42 of thedicing area 45 and moved in the direction of the silicon substrate 12while predetermined pressure is being applied along the surface a to becut off. At this time, the cut-in depth of the blade is gradually madedeep so as to reach the depth at which the main surface 12 a of thesilicon substrate 12 is exposed (see FIG. 3(A)). Incidentally, asblade's alignment, for example, a mark (not shown) can be formed at eachedge of the wafer formed with no encapsulating layer 42.

Thereafter, the ultraviolet cured acrylic resin of the dicing sheet 85is irradiated with ultraviolet radiation or light and thereby cured.Afterwards, the base material portion is extended in a predetermineddirection, and gaps or clearances are defined between the cut respectiveWCSPs 10 (see FIG. 3(B)). While such a state is being maintained, aforce is applied from the back surface of the dicing sheet 85 toindividually raise up the WCSPs 10 under pressure, followed by peelingof the individual WCSPs 10 from the dicing sheet.

Each of the peeled-off WCSPs 10 has a structure in which a side face (oralso called “side end face”) m of the encapsulating layer 42 is formedinside a side face n of the silicon substrate 12. This results from thefact that the side face m of the encapsulating layer 42 is a cut surfaceformed by the blade, whereas the side face n of the silicon substrate 12is a cut surface formed by the crack formed based on the modifiedportion formed by irradiation of the laser light. Let's assume that inthe present configurational example, e.g., blade dicing in which theinterval or spacing of a cut surface formed by cutting ranges from 50 μmto 200 μm, and laser dicing in which the interval or spacing of a cutsurface formed by cutting ranges from 0.2 μm to 4.0 μm are used. In sucha case, the side face m is formed inside the side face n within a rangeof 5 μm to 100 μm.

As is apparent from the above description, the cutting of the siliconsubstrate in each dicing area is performed using the laser dicing of theunheated system (or also called “non-melting system”) in the presentembodiment. In the laser dicing of the unheated system, the cut membercan be cut without almost producing cracks and chipping-off therein, andhigh-speed dicing is enabled as compared with the conventional dicingmethod using the blade.

It is, therefore, possible to suppress the occurrence of cracks andchipping-off in the silicon substrate in each dicing area due to theshock of the blade at dicing as in the prior art.

Thus, since damage of each through portion provided in the siliconsubstrate in each dicing area can be relaxed, an improvement in thereliability of each cut-out WCSP can be expected.

Further, since the distance between the surface a to be cut off and itscorresponding through portion can be shortened, there is no need toexpand the interval or spacing of each through portion between theadjacent packages in the wafer, i.e., the width of the dicing area ascompared with the conventional one in order to avoid the damage of eachthrough portion due to the dicing.

Therefore, the WCSPs each having high reliability and productivity canbe fabricated without reducing the number of the WCSPs cuttable perwafer.

Further, the WCSPs according to the present embodiment are capable ofconfiguring a laminated package by laminating the same in theirthickness directions.

<Second Embodiment>

A second embodiment of the present invention will be explained withreference to FIG. 4. FIGS. 4(A) and 4(B) are respectivelycross-sectional views for describing a semiconductor device according tothe present embodiment and its manufacturing method. Incidentally,components identical to those already described in the first embodimentare respectively identified by the same reference numerals, and theirspecific description will be omitted (respective embodiments to bedescribed below are also similar to above).

The present embodiment is principally different from the firstembodiment in that an encapsulating layer 42 is cut to a depth midwaythrough the encapsulating layer 42 as viewed from the surface 42 a sideof the exposed encapsulating layer 42, followed by being cleaved for itscutting.

Described specifically, process steps up to the cutting of the siliconsubstrate 12 are carried out by a method similar to the first embodiment(see FIG. 2(B)).

Thereafter, in the present embodiment, a cut-in depth made by a blade isset to a depth midway through the encapsulating layer 42 as viewed fromthe surface 42 a of the encapsulating layer 42 upon cutting theencapsulating layer 42, and trenches 88 are cut into the encapsulatinglayer 42 (see FIG. 4(A)). Incidentally, the cut-in depth made by theblade at this time may be set to a depth at which the encapsulatinglayer 42 portion is cuttable by cleavage in a post-process. However, theblade's cut-in depth may more preferably be set so as to be positionedabove a first wiring layer 26. By shallowly setting, in this way, thecut-in depth within a range in which the encapsulating layer can be cutoff by cleavage, the occurrence of cracks caused by vibrations of awafer at its dicing in the components such as the first wiring layer,etc. as well as in through portions can be effectively suppressed.

An ultraviolet cured acrylic resin of a dicing sheet 85 is thereafterirradiated with ultraviolet radiation or light and thereby cured.Afterwards, a base material portion is extended in a predetermineddirection to thereby cleave the encapsulating layer 42 portion leftbehind without being cut. Each WCSP 100 is peeled from the dicing sheet85 by a method similar to the first embodiment (see FIG. 4(B)).

At this time, a side face (or also called “side end face”) m₁ formed bycleavage, of a side face m on the encapsulating layer 42 side in eachpeeled WCSP 100 extends out outside a side face m₂ formed by the blade.A step portion 60 is formed at the boundary between the side face m₁ andthe side face m_(2.) Preferably, the step portion 60 is set such thatthe cut-in depth made by the blade is located above the first wiringlayer 26 as described above, and the step portion 60 may preferably beformed above the first wiring layer 26.

As is apparent from the above description, the present embodiment iscapable of obtaining an effect similar to the first embodiment.

Further, according to the present embodiment, the cutting of theencapsulating layer in the neighborhood of the silicon substrate isperformed by cleavage without being performed by dicing using the blade.

Thus, it is possible to further relax shock of the blade against thesilicon substrate in each dicing area and much further suppress thedamage of each through portion.

As a result, the width of the dicing area can further be narrowed ascompared with the first embodiment, and the fabrication of each higherreliable WCSP can be expected.

<Third Embodiment>

A third embodiment of the present invention will be explained withreference to FIGS. 5 through 7. FIG. 5 is a bottom view schematicallyshowing part of a wafer prior to being diced into semiconductor deviceseach according to the present embodiment. FIG. 6(A) is a cross-sectionalview as seen in the direction indicated by arrows in the figure, of acut-away portion obtained by cutting FIG. 5 along the dashed line VI—VI.FIGS. 6(B) to 7(B) are respectively cross-sectional views following FIG.6(A), for describing the semiconductor device according to the presentembodiment and a method of manufacturing the same.

The present embodiment is principally different from the firstembodiment in that the present invention is applied to a semiconductordevice of an SOI structure having an SOI (Silicon On Insulator)substrate as a substrate.

The semiconductor device having the SOI structure includes an SOIsubstrate of a three-layer structure in which each semiconductor layer(e.g., silicon single crystal layer) formed with circuit elements via aninsulating film interposed therebetween is provided on a semiconductorsupport substrate, and is excellent in high-speed operation and lowpower consumption. Since the circuit design and mask design of theconventional product can be applied as they are upon fabrication of thesemiconductor device having the SOI structure, the semiconductor deviceis excellent even in cost and reliability. On the other hand, there is aneed to fix the potential of the semiconductor support substrate to aground potential upon adoption of the SOI structure. This is becausethere is a fear that since the support substrate leads to parasiticcapacitance and resistive components although being isolated by aninsulating film, they will make unstable the electric characteristics ofthe semiconductor device. Therefore, when a chip equipped with the SOIsubstrate is applied to a BGA (Ball Grid Array) structure, for example,the support substrate side of the chip is mounted on and fixed to apredetermined position on a wiring substrate capable of being madeconductive to a ground terminal.

On the other hand, although the application of the SOI structure to eachWCSP is expected, problems mentioned below arise upon fixing thepotential of the support substrate to the ground potential.

Firstly, there is a method of electrically connecting a supportsubstrate of an SOI chip and a mounting board in a configuration inwhich the semiconductor layer side of the SOI chip is mounted on themounting board. However, according to the present method, there is aneed to ensure a new space for providing an electrical connection to theSOI chip on the mounting board side. Therefore, it is unfit forhigh-density packaging.

Secondly, there is a method of electrically connecting ground padsprovided on a semiconductor layer of an SOI chip and a support substrateby vias defined in a circuit element forming area of the chip. However,according to the present method, there is a need to change circuitdesign and mask design or the like with the formation of new vias. As aresult, there is a possibility that the method will incur an increase inpackage size as well as a need for a new wafer process. This method isnot satisfied in terms of cost and reliability.

The patent document 1 has the fear that since the wafer isfractionalized every packages by dicing using the blade although theconfiguration in which the SOI structure is applied to each WCSP, istaken, degradation of reliability due to the shock of the blade at theabove dicing will take place.

Therefore, the present embodiment will explain below WCSPs each having ahigh-reliable SOI structure without expanding a package size than ever.

The present embodiment will explain, by way of example, a packagestructural body 95 from which each WCSP 150 is cut out, as a processedobject that needs a dicing process.

Fist of all, as shown in FIG. 5, a wafer-shaped package structural body95 (to be described later) in which process steps up to the formation ofexternal terminals 34 on the obverse and reverse sides of an object tobe processed have been completed, is prepared as the object. Sub areas35 cut out as WCSPs 150 (see FIG. 6(C)) via an individualizing processto be described later are formed in the package structural body 95 inmatrix form.

Described specifically, peripheral edge portions of a surface area ofeach sub area 35 are peripheral areas (or also called dicing areas) 45having predetermined widths including cut surfaces a fractionalizedevery WCSPs 150. An area surrounded by the dicing areas 45 of each subarea 35 is a central area (or also called “circuit element formingarea”) 40 provided with circuit elements. Electrode pads 14 are disposedalong the outer periphery of the circuit element forming area 40 everypredetermined intervals. Here, the electrode pads 14 include ones thatfunction as ground pads 141 electrically connected to embedded portions(or also called “vias”) 98 (they will be described later). Also theelectrode pads 14 are electrically connected to their correspondingsolder balls 34 via a dedicated first wiring layer 26 that extendstoward the inside of the circuit element forming area 40. The embeddedportions (or also called “vias”) 98 (to be described later) included inthe adjacent sub areas 35 are respectively placed in opposingrelationship at positions which interpose plane or surfaces a to be cutoff at the dicing areas 45. Subsequently, the package structural body 95will be explained with reference to FIG. 6(A).

Electrode pads 14 made of aluminum, which are electrically connected totheir corresponding circuit elements, are formed on a main surface 106 aof a semiconductor layer 106 that constitutes an SOI substrate 108 ineach circuit element forming area 40. The SOI substrate 108 has aconfiguration in which the semiconductor layers 106 formed with thecircuit elements are sequentially formed on a semiconductor supportsubstrate 102 with an insulating film 104 interposed therebetween. Inthe present embodiment, the support substrate 102 is configured as asilicon substrate, the insulating film 104 is configured as a siliconoxide film, and the semiconductor layer 106 is configured as amonocrystal silicon layer.

Further, the embedded portions 98 are conductive columnar portions eachformed from the main surface 106 a of the semiconductor layer 106 ineach dicing area 45 to a depth (i.e., height) extending to a portionmidway through the support substrate 102. The potential of the supportsubstrate 102 can be fixed to a ground potential by the embeddedportions 98. As a result, the electric characteristics of each WCSP 150,which is cut out via a subsequent fractionalizing process, can bestabilized. Each of the embedded portions 98 is obtained by, forexample, firstly forming; by a drill or the like, a trench portion (oralso called “concave portion”) 99 so as to reach a depth extending fromthe surface 106 a of the semiconductor layer 106 to a portion midwaythrough the support substrate 102 and thereafter coating the boundary ofthe concave portion 99 and the semiconductor layer 106 with aninsulating film 56 by use of an insulating material (not shown),followed by formation of a conductive member 57 such as copper on thecorresponding insulating film 56 by plating.

Each of the ground pads 141 used in the present embodiment iselectrically connected to one end of the embedded portion 98 and one endof a post portion 28 constituting a wiring portion 32 via a first wiringlayer 26 used as a wiring pattern constituting the wiring portion 32formed on a first insulating layer 20. That is, the wiring portion 32 inthe present configurational example comprises the first wiring layer 26extending in the direction parallel to the main surface 106 a of eachsemiconductor layer 106, and the post portion 28 that protrudes in thedirection normal to the main surface 106 a so as to be located on thefirst wiring layer 26. As a whole, each wiring portion 32 constitutes aconvex portion that protrudes in the direction normal to the mainsurface 106 a. One end of the wiring portion 32 is connected to itscorresponding electrode pad 14 or ground pad 141, and the top face ofthe other end thereof is exposed without being covered with anencapsulating layer 42 to be described later. Incidentally, the firstwiring layer 26 is formed of copper (Cu) and functions even as aredistribution wiring layer capable of redistributing or relocating thecorresponding post portion 28 at a desired position as alreadymentioned. The encapsulating layer 42 is formed over the whole surface106 a of the semiconductor layer 106 with such a thickness as to exposethe top face of each post portion 28. Each of solder balls 34 is formedon its corresponding top face of the post portion 28, which is exposedfrom the encapsulating layer 42.

Subsequently, the solder balls 34 included in the wafer-shaped packagestructural body 95 are fixed onto a dicing sheet 65 in a manner similarto the first embodiment.

Thereafter, since the SOI substrate 108 has permeability with respect tolaser light, the cutting of the SOI substrate is performed using anon-melting system (or also called “unheated processing system”) usingthe laser light in a manner similar to the first embodiment (see FIG.6(B)).

A modified portion 110 caused by multiple photon absorption is formed bylaser light gathered inside the SOI substrate 108 with high accuracy ina manner similar to the first embodiment even at this time. At thistime, a crack 112 with the modified portion 110 as its starting pointoccurs due to internal stress and distortion with the formation of themodified portion 110. Thus, the SOI substrate 108 can be cut using thecrack 112 generated along the surface a to be cut off in each dicingarea 45.

Thereafter, the package structural body 95 is peeled from the dicingsheet 65 in a manner similar to the first embodiment. Afterwards, theback surface 95 b side on the SOI substrate side, of the packagestructural body 95 is fixed onto a new dicing sheet 85 in which abonding material is applied onto a base material surface.

Thereafter, the cutting of the encapsulating layer 42 is performed usinga blade rotated at high speed (see FIG. 7(A)). Afterwards, gaps orspacing are defined among the cut respective WCSPs 150 and thereby theindividual WCSPs 150 are peeled off (see FIG. 7(B)). Incidentally, thedepth at which the encapsulating layer 42 is cut off by the blade, isset to a position placed above the first wiring layer 26 as in thesecond embodiment even in the case of the present configurationalexample. Such a configuration that the encapsulating layer 42 is cut offby cleavage, may be adopted.

As is apparent from the above description, the cutting of the SOIsubstrate in the dicing areas is carried out by the laser dicing of theunheated system in the present embodiment.

It is, therefore, possible to suppress the occurrence of cracks andchipping-off in the SOI substrate in each dicing area due to the shockof the blade at dicing.

Thus, since damage of each embedded portion provided in the SOIsubstrate in each dicing area can be relaxed, an improvement in thereliability of each cut-out WCSP can be expected.

Further, according to the present embodiment, each cut WCSP is mountedto a mounting board so that a ground potential supplied from terminalsformed on the mounting board side to external terminals (solder balls)can be transmitted to the SOI substrate.

Described specifically, a transmission path used to supply a substratepotential from each of solder balls to each of embedded portions via acommon electrode pad connected to an electrode pad and a redistributionwiring layer, or a transmission path used to supply a substratepotential from each of solder balls to each of embedded portion via adedicated post portion and a redistribution wring layer is formed. Thus,this makes it possible to suppress unstability of the electriccharacteristics of each WCSP, which occurs due to parasitic capacitanceand resistive components of a support substrate.

Further, according to the present embodiment, the embedded portionsconnectable to the ground pads electrically connected to the solderballs 34 each supplied with the ground potential via the redistributionwiring layers used in the WCSP's structure can be formed in each dicingarea placed outside the area that functions as each SOI chip inpractice. Thus, since there is no need to change circuit design and maskdesign relative to the SOI chip side, the present embodiment isexcellent in cost and reliability.

Owing to the provision of the embedded portions in the dicing area, theWCSPs each having the SOI structure can be realized without expanding apackage size than ever.

Therefore, SOI substrate-adaptable WCSPs each having high reliabilityand productivity can be fabricated without reducing the number of WCSPscuttable per wafer.

As described above, the present invention is not limited to only thecombination of the above-mentioned embodiments. Thus, the presentinvention can be applied by utilizing suitable conditions in combinationat an arbitrary and suitable stage.

For instance, the dicing method of the unheated processing system usingthe laser light is not limited to only the above-mentioned method. Thus,an unheated processing system (or also called “non-melting system”)using various laser lights can be applied according to purposes anddesign.

Although the above embodiment has explained, by way of example, thewafer-shaped object to be processed prior to being fractionalized intothe WCSPs, the present invention is not limited to it. That is, thepresent invention can be applied to a processed object that needs tomake cutting between packages in which through portions are formed intheir peripheral edge portions. The shape of the object at this time isnot limited to only the round shape but may be set to a rectangularshape, for example.

Although the ultraviolet cured acrylic resins have been used as theadhesive materials for fixing the processed objects in the respectiveembodiments referred to above, each of the embodiments may take aconfiguration using wax or the like. No limitation is imposed on thefixing of the object by the dicing sheet. For instance, a fixing jig maybe used.

Although the above-described embodiment has explained, as an example,the case in which the silicon substrate is used as the semiconductorsubstrate, the present invention is not limited to it. For instance, anSOS (Silicon On Sapphire) substrate in which a silicon thin film isformed on a sapphire layer, may be used. In this case, a dicing timeinterval relative to the sapphire layer corresponding to a hard-to-cutmaterial high in hardness can be greatly shortened as compared with thedicing using the blade.

In the respective embodiments, the dicing using the blade has beencarried out after the execution of the laser dicing of the unheatedsystem. However, the order of the individual dicing may be set inreverse according to purposes and conditions or the like.

While the present invention has been described with reference to theillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications of the illustrativeembodiments, as well as other embodiments of the invention, will beapparent to those skilled in the art on reference to this description.It is therefore contemplated that the appended claims will cover anysuch modifications or embodiments as fall within the true scope of theinvention.

1. A semiconductor device, comprising: a substrate which has a mainsurface including a central area formed with a circuit element and anelectrode pad connected to the circuit element and a peripheral areasurrounding the central area, which has a back surface opposite to themain surface, and which has a through hole defined in the peripheralarea and extending from the main surface to the back surface; aninsulating film formed on an inner wall of the through hole; aconductive member provided on the insulating film within the throughhole and electrically connected to the circuit element; an externalterminal provided above the main surface; a wiring portion whichconnects the external terminal and the electrode pad; and anencapsulating layer which covers the main surface and the wiring portionexcept for a portion to which the external terminal is connected,wherein a side surface of the encapsulating layer is formed inside aside surface of the substrate.
 2. A semiconductor device according toclaim 1, wherein the wiring portion includes a wiring pattern extendingin the direction parallel to the main surface of the substrate and aconductor portion connected to the external terminal, and the conductivemember and the circuit element is electrically connected via the wiringpattern.
 3. A semiconductor device according to claim 1, wherein thesubstrate is a silicon substrate or a sapphire substrate whose surfaceis formed with a silicon thin film.
 4. A semiconductor device accordingto claim 1, wherein the side surface of the encapsulating layer isformed with cut surface cut by a blade, and the side surface of thesubstrate is formed with a cut surface cut by laser light.
 5. Asemiconductor device according to claim 4, wherein the side surface ofthe encapsulating layer is formed with a step portion.
 6. Asemiconductor device according to claim 5, wherein the step portion islocated between the wiring pattern and the surface of the encapsulatinglayer.
 7. A semiconductor device, comprising: a substrate which has asemiconductor support substrate, an insulating film formed on thesemiconductor support substrate, and a semiconductor layer formed on theinsulating film, said semiconductor layer having a main surfaceincluding a central area formed with a circuit element and an electrodepad connected to the circuit element and a peripheral area thatsurrounds the central area; a trench portion defined in the peripheralarea, which extends from the main surface of the substrate to thesupport substrate; a conductive member provided within the trenchportion and electrically insulated from the semiconductor layer, saidconductive member being electrically connected to the circuit elementand the semiconductor support substrate; an external terminal providedabove the main surface; a wiring portion that electrically connectsbetween the external terminal and the electrode pad; and anencapsulating layer that covers the main surface and the wiring portionexcept for a portion to which the external terminal is connected,wherein a side surface of the encapsulating layer is formed inside aside surface of the substrate.
 8. A semiconductor device according toclaim 7, wherein the wiring portion includes a wiring pattern extendingin the direction parallel to the main surface of the substrate and aconductor portion connected to the external terminal, and the conductivemember and the circuit element are electrically connected via the wiringpattern.
 9. A semiconductor device according to claim 7, wherein theside surface of the encapsulating layer is formed with a cut surface cutby a blade, and the side surface of the substrate is formed with a cutsurface cut off by laser light.